In order to build faster and more complex integrated circuits, semiconductor manufacturers have increased the number of components in the integrated circuit while reducing the overall size of the circuit. The small circuit size requires multiple overlying metal layers to electrically interconnect the vast number of components within the integrated circuit. As successive layers of conductors and dielectric materials are deposited over previously defined structures, the surface topography can become uneven. Also, advanced circuits incorporate embedded conductive metal leads formed in inlay patterns within an insulating layer. The pattern density can vary widely across different regions of the circuit.
To be manufactured reliably, the metal layers need to be deposited, and an interconnect pattern defined on a smooth, planar surface. A planarization process is typically performed after the deposition of an insulating layer to reduce the topographic contrast of the insulating layer. A conductive layer is then deposited on a smooth, even surface and the interconnect pattern reliably defined using conventional photolithography. In a process to form an inlaid metal layer, an inlay pattern is formed in the insulating layer and a metal is deposited over the insulating layer. The metal layer and the insulating layer are subjected to a planarization process to produce a smooth surface.
One method for planarizing the substrate surface during integrated circuit fabrication is a polish planarization process. Chemical-mechanical-polishing (CMP) processes have been developed which abrasively removed elevated portions of both insulating materials and metals. In this process, the surface of the substrate is brought into contact with a polish pad covered with liquid polishing slurry. A portion of the insulating or metal layer is then removed by the mechanical action of the polish pad and the chemical action of the slurry.
A common requirement of all polishing processes is that the substrate be uniformly polished. Uniform polishing can be difficult because, typically, there is a strong dependence in the polish removal rate with localized variations in the surface topography of the substrate. For example, in substrate areas having a high degree of surface variation, such as areas having closely spaced adjacent trenches, the polishing rate is higher than in areas lacking a high degree of surface contrast, such as areas having large active device regions. The variation in polish removal rate caused by feature density variation results polishing process effects know as dishing and erosion. To avoid the effects of dishing and erosion, the polishing time can be extended beyond that required to just remove the metal or insulating layer from the most elevated regions. The polish time cannot be extended indefinitely, however, or layers underlying the insulating layer can be damaged.
While potentially offering wide versatility and a high degree of uniformity, the polish process must be controlled to avoid generating an uneven surface and damaging underlying layers. This problem has been made more difficult by the recent development of abrasive-free polishing slurries. Accordingly, a need exists for an improved polishing process that is less sensitive to feature density variations across device circuits and supporting substrates.